The present invention relates generally to signal transmission lines built on silicon wafers for the purpose of wafer-scale integration, and more particularly to micro-strip signal transmission lines for programmable interconnection wafers which are constructed to optimize signal transmission speeds.
In the past, integrated circuit (IC) chips were electrically connected together through the use of "pin" packages and printed circuit boards. Each IC chip would first be mounted in the cavity of a separate pin package which had to be large enough to provide a number of sturdy pin connections. Then, these IC chips containing packages would be mounted to a printed circuit board which was designed to provide a specific pattern of electrically conductive paths necessary to interconnect the pins of these packages together in the desired way.
While this technique of interconnecting IC chips together has been used for many years, it has several drawbacks. In the first place, it takes up far too much room. Since the IC chips themselves occupy only a very small amount of a typical pin package, and the pin packages must be separated on the circuit board, a great deal of wasted space is built in to each multi-chip circuit design. While the amount of this wasted space can be reduced by integrating more transistors into each IC chip, eventually the designer will be faced with the need to interconnect various IC chips together in order to achieve a unique circuit design. Accordingly, achieving higher densities within each chip only addresses one aspect of the wasted space problem. The interconnection between discrete IC chips must still be addressed in order to provide a truly dense circuit design.
It will also be appreciated that substantial costs are associated with this type of low density interconnection technique. Each circuit board has to be individually designed to provide a printed pattern of conductive paths which is appropriate to the size, type and number of IC chips contained on the circuit board card. Additionally, a separate pin package must be provided for each IC chip manufactured, and these pin packages may also have to be designed specifically for its intended IC chip.
Perhaps the most important consideration involved in interconnecting IC chips together in one of time. Since the conductive paths through the pin packages and the circuit board are relatively long, the operation of the IC chips is constrained by the time it takes for signals to be transmitted between the IC chips. Accordingly, if the length of these conductive paths can be reduced, then the transmission delays can also be reduced as well. This consideration is particularly important in the field of super computers where processing speed and heat dissipation are paramount considerations.
In order to decrease the distance between IC chips, "thick film" ceramic circuit boards have been proposed. While such circuit boards permit the mounting of IC chips directly to the ceramic substrate of these boards, the layout of conductive paths for these circuit boards still need to be individually designed for each application. Additionally, the density of the number of IC chips per circuit board area is limited by the nature of the pattern of conductive paths which is typically formed on a single layer of the ceramic substrate.
A further advance toward the goal of providing dense interconnections between IC chips has recently been realized through the use of a universally programmable silicon circuit board (SCB). An SCB is a standardized, electrically programmable interconnect system which is formed on a silicon wafer or substrate. An SCB can be characterized as "thin film" circuit board technology, due to the fact that the conductive paths have dimensions in the micron region. The SCB permits a product designer to mount diverse IC chips and hybrid components directly to a very compact silicon substrate which acts as a circuit board. No pin packages are required, and the SCB can be programmed electronically so that a single SCB design can serve a wide variety of multi-chip circuit designs.
Each SCB includes a matrix of orthogonal metal lines which are disposed on distinct planes. These planes are separated at crossovers by an amorphous silicon material which normally has a high resistance. However, this layer of amorphous silicon is designed to operate as an "anti-fuse" in that selected electrical connections can be made between the metal lines on different planes. Specifically, when a threshold voltage is applied to the amorphous silicon, the material will switch from a high resistance value to a low resistance value at a desired interconnection point. This "anti-fuse" capability of the amorphous silicon allows many thousands of possible interconnections to be made between various metal lines of the SCB matrix, and hence a host of different IC chip interconnections can be readily made using automated programming techniques.
In addition to the above, other advantageous features of the SCB include the ability to mount the IC chips to the substrate through conventional wire bonding techniques, and temperature matching of silicon IC chips with the silicon substrate to reduce stress and fatigue. The integrity of the interconnection network can also be automatically tested, and faults can be readily corrected by programming alternate routes through the network. The electrical programming of the network by firing the appropriate "anti-fuses" can be accomplished within hours, so that a design engineer does not have to wait long periods of time for masks to be developed and the line.
A further general discussion of SCBs may be found in the following references: U.S. Pat. No. 4,467,400, issued on Aug. 21, 1984 to Herbert Stopper, entitled "Wafer Scale Integrated Circuit"; U.S. Pat. No. 4,479,088, issued on Oct. 23, 1984 to Herbert Stopper, entitled "Wafer Including Test Lead Connected To Ground For Testing Networks Thereon"; U.S. Pat. No. 4,458,297, issued on July 3, 1984 to Herbert Stopper et. al., entitled "Universal Interconnection Substrate"; and an article entitled "A Wafer With Electrically Programmable Interconnections", 1985 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 268-269. These references and hereby incorporated by reference.
As will be discussed further below, the metal lines of the SCB may approach the "lossy line" transmission characteristics of a Thomson Cable. This lossy line characteristic has the advantage of eliminating the need for terminating resistors. However, this characteristic can also result in undesirable transmission delays through the interconnection network. Specifically, for homogeneous metal lines in an SCB network, this delay has been found to be proportional to the square of the length. Accordingly, it should be appreciated that the length of the SCB signal transmission lines can become an important design consideration when extremely high processing speeds are desired. Thus, on one hand, long signal transmission lines can facilitate the interconnection of many IC chips on a single SCB. However, on the other hand, it is possible that such long signal transmission lines may not be consistent with achieving the goal of maximizing the overall processing speed for multi-chip circuits and other micro-electronic circuits.
Accordingly, it is a principal objective of the present invention to provide an interconnection method and apparatus for increasing signal transmission speeds through micro-electronic circuits.
It is a more specific objective of the present invention to provide an improved SCB transmission line network geometry which approaches an almost linear relationship between the length of the transmission line and the signal delay through the transmission line.
It is another objective of the present invention to provide an interconnection method and apparatus which maximizes the signal transmission speed over a given distance, such that over this distance the transmission line is capable of modeling the signal transmission characteristics of a coaxial "lossless" transmission line.
It is a further objective of the present invention to provide a method and apparatus for increasing signal transmission times which achieves an optimum relationship between total resistance of the transmission line and its characteristic impedance.
It is an additional objective of the present invention to provide a plurality of micro-strip transmission line structures which can be readily fabricated and interconnected together in combination to achieve a high speed signal transmission path.
It is yet another objective of the present invention to provide a high speed transmission path for use in a variety of micro-electronic circuit applications, including applications with signal frequencies above 1GH.sub.z.
It is still another objective of the present invention to create a high speed transmission path which provides an optimized termination resistor effect that is distributed along the transmission path.